fn4311 rev 9.00 page 1 of 8 march 2004 fn4311 rev 9.00 march 2004 HIP1011 pci hot plug controller datasheet the HIP1011 is the pci hot plug voltage bus control ic for use in modern computer syste ms that facilitates hot plugging of adapter cards into and ou t of an active o r passive back plane. along with discrete power mosfets and a few passive components, the HIP1011 creat es a small and simple yet complete power control solution. four independent supplies are controlled, +5v, +3.3v, +12 v, and -12v. the +12v and - 12v switches are integrated. f or the +5v and +3.3v supplies, overcurrent protection is pro vided by sensing the voltage across external current-sense resistors. for the +12v and -12v supplies, overcu rrent protection is pro vided internally. i n addition, an on-chip reference is used to monitor the +5v, +3.3v and +12v outputs for undervoltage conditions. the pwron input controls the state of the switches. during an overcurrent condition on any output, or an undervoltage condition on the +5v, +3.3v or +12v outputs, all mosfets are immediately latched-off a nd a low (0v) is asserted on the fltn output. the fltn latch is cleared when the pwron input is toggled low again. during initial power-up of the main v cc supply (+12v), the pwron i nput is inhibited from turning on the switches, and t he latch is held in the reset state until the v cc input is grea ter than 10v. user programmability of the overcurrent th reshold and turn-on slew rate is provided. a resis tor connected to the ocset pin programs the overcurrent threshol d. capacitors connected to the gate pins set the turn-on ra te. also, a capacitor may be added to the fltn pin to provide noise immunity. features ? controls distribution of four supplies: +5v, +3.3v, +12v, and -12v ? internal mosfet switches fo r +12v and -12v outputs ? microprocessor interface fo r on/off control and fault reporting ? adjustable overcurrent pr otection for all supplies ? provides fault isolation ? adjustable turn-on slew rate ? minimum parts count solution ? no charge pump ? pb-free package options applications ? pci hot plug ? compactpci pinout HIP1011 (soic) top view ordering information part number temp. range (c) package pkg. dwg. # HIP1011cb 0 to 70 16 ld soic m16.15 HIP1011cb-t 0 to 70 tape and reel HIP1011cbza (note) 0 to 70 16 ld soic (pb-free) m16.15 HIP1011cbza-t (note) 0 to 70 tape and reel (pb-free) HIP1011eval1 evaluation platform note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb an d pb-free soldering operations. in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020b. 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 m12vin fltn 3v5vg v cc 12vin 3visen ocset 3vs m12vo 12vg gnd 12vo m12vg 5visen 5vs pwron no t r e c o m m e n de d f o r n e w de s i g n s n o r e co m m e nd e d r e p l ac e m e n t c o n t a c t o u r t e c h n ic a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s il . c o m / t s c
HIP1011 fn4311 rev 9.00 page 2 of 8 march 2004 typical application 12v, m12vin fltn 3v5vg v cc 12vin 3visen 3vs ocset m12vo 12vg gnd 12vo 5visen 5vs pwron m12vg HIP1011 3.3v, 12v input 5v, -12v, 5v input -12v input power control input 0.033f 0.033f 6.04k ? fault output (active low) (optional) 5m ? , 1% 0.033f note: 1. all capacitors are ? 10%. 1% 3.3v input 5m ? , 1% 7.6a out 0.5a out 0.1a out 5a out huf761315k8
HIP1011 fn4311 rev 9.00 page 3 of 8 march 2004 simplified schematic fltn 5vs 3v5vg 5visen 3vs ocset 3visen 12vin 12vg 12vo m12vin m12vg m12vo pwron gnd 12vin power-on reset v cc m12vin v cc v cc 100a 0.3 ? 0.7 ? fault latch v ocset 5v zener reference v cc 5vref 5vref v ocset /17 v ocset /0.8 4.6v inhibit v cc set (low = fault) reset v cc low = fault low when v cc < 10v high = switches on high = fault + - comp - + comp - + v ocset /13.3 + - comp + 2.9v inhibit comp + - 10.8v inhibit comp + - comp - + + - v cc v cc v ocset /3.3 comp - + + - -
HIP1011 fn4311 rev 9.00 page 4 of 8 march 2004 pin descriptions pin designator function description 1 m12vin -12v input -12v supply inpu t. also provides power to the -12v overcurrent circuitry. 2 fltn fault output 5v cmos fault output; low = fault. an optional capacitor may be place from this pin to ground to provide additional immuni ty from power supply glitche s. 3 3v5vg 3.3v/5v gate output drive the gates of the 3.3v and 5v mos fets. connect a capacitor to ground to set the startup ramp. during turn on, this capacitor is charged with a 25 ? a current source. 4 vcc 12v v cc input connect to unswitched 12v supply. 5 12vin 12v input switched 12v supply input. 6 3visen 3.3v current sense connect to the load side of the curren t sense resistor in series with source of external 3.3v mosfet. 7 3vs 3.3v source connect to source of 3.3v mosfet. this connecti on along with pin 6 (3visen) senses the voltage drop across the sense resistor. 8 ocset overcurrent set connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. all four over current trips can be programmed by changing the value of this resistor. the default (6.04k ?? 1%) is compatible with the maximum allowable currents as outli ned in the pci specification. 9 pwron power on control controls a ll four switches. high to turn switches on, low to turn them off. 10 5vs 5v source connect to source of 5v mosfet switch. this conne ction along with pin 11(5visen) senses the voltage drop across the sense resistor. 11 5visen 5v current sense connect to the load side of the current sense resistor in series with source of external 5v mosfet. 12 12vo switched 12v output switched 12v output. 13 gnd ground connect to common of power supplies. 14 12vg gate of internal pmos connect a capacitor between 12vg and 12vo to set the startup ra mp for the +12v supply. this capacitor is charged with a 25 ? a current source during startup. the 3.3v and 5v uv circuitry is enabled after the voltage on 12vg is less than 400mv. theref ore, if the capacitor on the pin 3 (3v5vg) is more than 25% larger than the capacitor on pin 14 (12vg) a false uv may be detected during startup. 15 m12vg gate of internal nmos connect a capacitor between m12vg and m12vo to set the startup ramp for the m12v supply. this capacitor is charged with 25 ? a during startup. 16 m12vo switched -12v output switched 12v output.
HIP1011 fn4311 rev 9.00 page 5 of 8 march 2004 absolute maximum ratings thermal information v cc , 12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0v 12vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v 12vin +0.5v 12vo, 12vg, 3v5vg . . . . . . . . . . . . . . . . . . . . . -0.5 v to v cc +0.5v m12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0v to +0.5v m12vo, m12vg. . . . . . . . . . . . . . . . . . . . . v m12vin -0.5v to +0.5v 3visen, 5visen . . . . . . . . . . . -0.5v to the lesser of v cc or +7.0v voltage, any other pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kev (hbm) operating conditions vcc supply voltage range. . . . . . . . . . . . . . . . . +10. 8v to +13.2v ? 12v, 5v and 3.3v input supply tolerances . . . . . . . . . . . . . . ? 10% 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.5a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.1a temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c thermal resistance (typical, note 1) ? ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 125c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c (soic - lead tips only) die characteristics number of transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board in free air. see techn ical brief 379 for details. 2. all voltages are relative to g nd, unless otherwise specified. electrical specifications nominal 5v and 3.3v input supply voltages, v cc = 12vin = 12v, m12vin = -12v, t a = t j = 0 to 70c, unless otherwise specified parameter symbol test conditions min typ max units 5v/3.3v supply control 5v overcurrent threshold i oc5v see figure 1, typical application - 7.1 - a 5v overcurrent threshold voltage v oc5v v ocset = 1.2v 66 72 79 mv 5v undervoltage trip threshold v 5vuv 4.42 4.6 4.75 v 5v undervoltage fault response time t 5vuv - 150 350 ns 5v turn-on time (pwron high to 5vout = 4.75v) c 3v5vg = 0.022 ? f, c 5vout = 2000 ? f, r l = 1 ? -6.5- ms 5vs input bias current ib 5vs pwron = high -40 -26 -20 ? a 5visen input bias current ib 5visen pwron = high -160 -140 -110 ? a 3v overcurrent threshold i oc3v see figure 1, typical application - 9.0 - a 3v overcurrent threshold voltage v oc3v v ocset = 1.2v 88 95 102 mv 3v undervoltage trip threshold v 3vuv 2.74 2.86 2.97 v 3v undervoltage fault response time t 3vuv - 150 350 ns 3v turn-on time (pwron high to 3vout = 3.00v) c 3v5vg = 0.022 ? f, c 3vout = 2000 ? f, r l = 0.43 ? -6.5- ms 3vs input bias current ib 3vs pwron = high -40 -26 -20 ? a 3visen input bias current ib 3visen pwron = high -160 -140 -110 ? a gate output charge current ic 3v5vg pwron = high, v 3v5vg = 2v 22.5 25.0 27.5 ? a gate turn-on time (pwron high to 3v5vg = 11v) t on3v5v c 3v5vg = 0.1 ? f - 280 500 ? s gate turn-off time t off3v5v c 3v5vg = 0.1 ? f, 3v5vg from 9.5 v to 1v - 13 17 ? s gate turn-off time c 3v5vg = 0.022 ? f, 3v5vg falling 90% to 10% -2- ? s
HIP1011 fn4311 rev 9.00 page 6 of 8 march 2004 +12v supply control on resistance of internal pmos r ds(on)12 pwron = high, i d = 0.5a, t a = t j = 25c 0.18 .300 0.350 ? overcurrent threshold i oc12v v ocset = 1.2v 1.25 1.50 1.8 a 12v undervoltage trip threshold v 12vuv 10.5 10.8 11.15 v undervoltage fault response time t 12vuv - 150 - ns gate charge current ic 12vg pwron = high, v 12vg = 3v 23.5 25.0 28.5 ? a turn-on time (pwron high to 12vg = 1v) t on12v c 12vg = 0.022 ? f - 16 20 ms turn-off time t off12v c 12vg = 0.1 ? f, 12vg - 9 12 ? s turn-off time c 12vg = 0.022 ? f, 12vg rising 10% - 90% -3- ? s -12v supply control on resistance of internal nmos r ds(on)m12 pwron = high, i d = 0.1a, t a = t j = 25c 0.5 0.7 0.9 ? overcurrent threshold i ocm12v v ocset = 1.2v 0.30 0.37 0.50 a gate output charge current ic m12vg pwron = high, v m12vg = -4v 22.5 25 27.5 ? a turn-on time (pwron high to m12vg = -1v) t onm12v c m12vg = 0.022 ? f - 160 300 ? s turn-on time (pwron high to m12vo = -10.8v) c m12vg = 0.022 ? f, c m12vo = 50 ? f, r l = 120 ? -16-ms turn-off time t offm12v c m12vg = 0.1 ? f, m12vg - 18 23 ? s turn-off time c m12vg = 0.022 ? f, m12vg falling 90% to 10% -3- ? s m12vin input bias current ib m12vin pwron = high - 2 2.6 ma control i/o pins supply current i vcc 455.8ma ocset current i ocset 95 100 105 ? a overcurrent fault response time t oc - 500 960 ns pwron threshold voltage v thpwron 0.8 1.6 2.1 v fltn output low voltage v fltn,ol i fltn = 2ma - 0.6 0.9 v fltn output high voltage v fltn,oh i fltn = 0 to -4ma 3.9 4.3 4.9 v fltn output latch threshold v fltn,th 1.8 2.3 3 v 12v power on reset threshold v por,th v cc voltage falling 9.4 10 10.6 v electrical specifications nominal 5v and 3.3v input supply voltages, v cc = 12vin = 12v, m12vin = -12v, t a = t j = 0 to 70c, unless otherwise specified (continued) parameter symbol test conditions min typ max units
HIP1011 fn4311 rev 9.00 page 7 of 8 march 2004 typical performance curves figure 1. r on vs temperature figure 2. uv trip vs temperature figure 3. 12 uv trip vs temperature figure 4. ocvth vs temperature (vr ocset = 1.21v) figure 5. ocset i vs temperature 340 320 300 280 260 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 1000 900 800 700 600 pmos r on +12 (m ? ) nmos r on -12 (m ? ) temperature (c) pmos +12 r on nmos -12 r on 4.632 4.631 4.630 4.629 4.626 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 5v uvtrip (v) 3.3v uvtrip (v) temperature (c) 5 uv 4.628 4.627 2.862 2.861 2.860 2.859 2.858 3.3 uv 10.84 10.83 10.82 10.81 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 12 uv trip (v) temperature (c) 100 90 80 70 60 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 oc vth (mv) temperature (c) 5v ocvth 3v ocvth 102 101 100 99 98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 ioc set ( ? a) temperature (c)
fn4311 rev 9.00 page 8 of 8 march 2004 HIP1011 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 ? 0 8 0 8 - rev. 1 02/02
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